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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. ts5usbc41 scds377 ? march 2018 ts5usbc41 dual 2:1 usb 2.0 mux/demux or single ended cross switch with 16-v/20-v overvoltage protection 1 1 features 1 ? supply range 2.3 v to 5.5 v ? differential 2:1 or 1:2 switch/multiplexer or flexible dual single ended cross switch ? 0-v to 16-v (ts5usbc410) and 20-v (ts5usbc412) overvoltage protection (ovp) on common pins ? powered off protection when v cc = 0 v ? low r on of 9 maximum ? bw of 1.1-ghz (ts5usbc410) and 1.2-ghz (ts5usbc412) typical ? c on of 4.5 pf typical ? low power disable mode ? 1.8-v compatible logic inputs ? esd protection exceeds jesd 22 ? 2000-v human body model (hbm) ? ts5usbc410 and ts5usbc412: standard temperature range of 0 c to 70 c ? ts5usbc410i and ts5usbc412i: industrial temperature range of -40 c to 85 c ? small dsbga package 2 applications ? mobile ? pc/notebook ? tablet ? anywhere a usb type-c ? or micro-b connector is used 3 description the ts5usbc41 is a bidirectional low-power dual port, high-speed, usb 2.0 analog switch with integrated protection for usb type-c ? systems. the device is configured as a dual 2:1 or 1:2 switch and is optimized for handling the usb 2.0 d+/- lines in a usb type-c ? systems. the ts5usbc41 protection on the i/o pins can tolerate up to 16 v (ts5usbc410) or 20 v (ts5usbc412) with automatic shutoff circuitry to protect system components behind the switch. the ts5usbc41 comes in a small 12 pin dsbga package making it a perfect candidate for mobile and space constrained applications. device information (1) part number package body size (nom) ts5usbc410 ts5usbc410i ts5usbc412 ts5usbc412i dsbga (12) 1.638 mm 1.238 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified schematic usb vcc d1- d2+ d1+ ovp logic control gnd vbus dp_t dp_b dm_t dm_b gnd usb connector uart usb d2- sel1sel2 oe flt advance information tools & software technical documents ordernow productfolder support &community
2 ts5usbc41 scds377 ? march 2018 www.ti.com submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 5 6.5 electrical characteristics ........................................... 5 6.6 dynamic characteristics ........................................... 7 6.7 timing requirements ................................................ 7 6.8 typical characteristics .............................................. 8 7 parameter measurement information .................. 9 8 detailed description ............................................ 13 8.1 overview ................................................................. 13 8.2 functional block diagram ....................................... 13 8.3 feature description ................................................. 14 8.4 device functional modes ........................................ 16 9 application and implementation ........................ 17 9.1 application information ............................................ 17 9.2 typical application .................................................. 17 10 power supply recommendations ..................... 18 11 layout ................................................................... 19 11.1 layout guidelines ................................................. 19 11.2 layout example .................................................... 20 12 device and documentation support ................. 21 12.1 documentation support ........................................ 21 12.2 community resources .......................................... 21 12.3 trademarks ........................................................... 21 12.4 electrostatic discharge caution ............................ 21 12.5 glossary ................................................................ 21 13 mechanical, packaging, and orderable information ........................................................... 21 4 revision history date revision notes march 2018 * initial release advance information
3 ts5usbc41 www.ti.com scds377 ? march 2018 submit documentation feedback copyright ? 2018, texas instruments incorporated 5 pin configuration and functions yff package 12-pin dsbga top view pin functions pin i/o description no. name a1 sel1 i switch select1 (active high) a2 d+ i/o data switch input (differential +). a3 d ? i/o data switch input (differential ? ) a4 flt o fault indicator output pin (active low) - open drain b1 vcc pwr supply voltage b2 sel2 i switch select2 (active high) b3 gnd gnd ground b4 oe i output enable (active low) c1 d2+ i/o data switch output 2 (differential +) c2 d2 ? i/o data switch output 2 (differential -) c3 d1+ i/o data switch output 1 (differential +) c4 d1 ? i/o data switch output 1 (differential -) advance information 1 2 3 4 a b c not to scale sel1 d+ d flt vcc sel2 gnd oe d2+ d2 d1+ d1
4 ts5usbc41 scds377 ? march 2018 www.ti.com submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. theseare stress ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under recommended operatingconditions . exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability. (2) the algebraic convention, whereby the most negative value is aminimum and the most positive value is a maximum. (3) all voltages are with respect to ground, unless otherwisespecified. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) min max unit v cc supply voltage (3) ? 0.5 6 v v i/o input/output dc voltage (d+, d-) (ts5usbc412, ts5usbc412i) (3) -0.5 20 v v i/o input/output dc voltage (d+, d-) (ts5usbc410, ts5usbc410i) (3) -0.5 16 v v i/o input/output dc voltage (d1+/d1-, d2+/d2-) (3) -0.5 6 v v i digital input voltage (sel1, sel2, oe) ? 0.5 6 v v o digital output voltage ( flt) ? 0.5 6 v i k input-output port diode current (d+, d-, d1+, d1-, d2+, d2-) when v in < 0 ? 50 ma i ik digital logic input clamp current (sel1, sel2, oe) when v i < 0 (3) ? 50 ma i cc continuous current through vcc 100 ma i gnd continuous current through gnd ? 100 ma t stg storage temperature ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safemanufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safemanufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 1000 6.3 recommended operating conditions min max unit v cc supply voltage 2.3 5.5 v v i/o (d+, d-) analog input/output voltage (ts5usbc412, ts5usbc412i) 0 20 v v i/o (d+, d-) analog input/output voltage (ts5usbc410, ts5usbc410i) 0 16 v v i/o (d1, d1-, d2+, d2-) analog input/output voltage 0 3.6 v v i digital input voltage (sel1, sel2, oe) 0 5.5 v v o digital output voltage ( flt) 0 5.5 v i i/o (d+, d-, d1+, d1-, d2+, d2-) analog input/output port continuous current -50 50 ma i ol digital output current 3 ma t a operating free-air temperature (standard) (ts5usbc410, ts5usbc412) 0 70 o c t a operating free-air temperature (industrial) (ts5usbc410i, ts5usbc412i) ? 40 85 o c t j junction temperature ? 40 125 o c advance information
5 ts5usbc41 www.ti.com scds377 ? march 2018 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for more information about traditional and new thermalmetrics, see the semiconductor and icpackage thermal metrics application report. 6.4 thermal information thermal metric (1) device unit yff 12 pins r ja junction-to-ambient thermal resistance 91.8 c/w r jc(top) junction-to-case (top) thermal resistance 0.8 c/w r jb junction-to-board thermal resistance 22.8 c/w jt junction-to-top characterization parameter 0.5 c/w jb junction-to-board characterization parameter 23.0 c/w 6.5 electrical characteristics t a = ? 40 c to +85 c (industrial), t a = 0 to 70 (standard),v cc = 2.3 v to 5.5 v, gnd = 0 v, typical values are at v cc = 3.3 v, t a = 25 c, (unless otherwise noted) parameter test conditions min typ max unit supply v cc power supply voltage 2.3 5.5 v icc active supply current oe = 0 v sel1, sel2 = 0 v, 1.8 v or v cc 0 v < v i/o < 3.6 v 10 22 a supply current during ovp condition oe = 0 v sel1, sel2 = 0 v, 1.8 v or v cc v i/o > v pos_thld 15 35 a i cc_pd standby powered down supply current oe = 1.8 v or v cc sel1 = 0 v, 1.8 v, or vcc sel2 = 0 v, 1.8 v, or vcc 2.2 6 a dc characteristics r on on-state resistance v i/o = 0.4 v i sink = 8 ma refer to on-state resistance figure 5.6 9 ? r on on-state resistance match between channels v i/o = 0.4 v i sink = 8 ma refer to on-state resistance figure 0.07 0.3 ? r on (flat) on-state resistance flatness v i/o = 0 v to 0.4 v i sink = 8 ma refer to on-state resistance figure 0.07 0.4 ? i off i/o pin off leakage current v d = 0 v or 3.6 v v cc = 2.3 v to 5.5 v v d1 or v d2+/- = 3.6 v or 0 v refer to off leakage figure -1 1 2 a v d = 0 v or 16 v v cc = 2.3 v to 5.5 v v d1 or v d2+/- = 0 v refer to off leakage figure -1 150 180 a i on on leakage current v d = 0 v or 3.6 v v d1 and v d2+/- = high-z refer to on leakage figure -1 1 2 a digital characteristics v ih input logic high sel1, sel2, oe 1.4 v v il input logic low sel1, sel2, oe 0.5 v v ol output logic low flt i ol = 3 ma 0.4 v i ih input high leakage current sel1, sel2, oe = 1.8 v, v cc -1 1 5 a i il input low leakage current sel1, sel2, oe = 0 v -1 0.2 5 a advance information
6 ts5usbc41 scds377 ? march 2018 www.ti.com submit documentation feedback copyright ? 2018, texas instruments incorporated electrical characteristics (continued) t a = ? 40 c to +85 c (industrial), t a = 0 to 70 (standard),v cc = 2.3 v to 5.5 v, gnd = 0 v, typical values are at v cc = 3.3 v, t a = 25 c, (unless otherwise noted) parameter test conditions min typ max unit r pd internal pull-down resistor on digital input pins 6 m c i digital input capacitance sel1, sel2 = 0 v, 1.8 v or vcc f = 1 mhz 3.4 pf protection v ovp_th ovp positive threshold 4.5 4.8 5.2 v v ovp_hyst ovp threshold hysteresis 150 250 350 mv v clamp_v maximum voltage to appear on d1 and d2 pins during ovp scenario (ts5usbc412, ts5usbc412i) v d = 0 to 18 v t rise and t fall (10% to 90 %) = 100 ns r l = open switch on or off oe = 0 v 0 9 v v clamp_v maximum voltage to appear on d1 and d2 pins during ovp scenario (ts5usbc412, ts5usbc412i) v d = 0 to 18 v t rise and t fall (10% to 90 %) = 100 ns r l = 50 ? switch on or off oe = 0 v 0 9 v v clamp_v maximum voltage to appear on d1 and d2 pins during ovp scenario (ts5usbc410, ts5usbc410i) v d = 0 to 16 v t rise and t fall (10% to 90 %) = 100 ns r l = open switch on or off oe = 0 v 0 9 v v clamp_v maximum voltage to appear on d1 and d2 pins during ovp scenario (ts5usbc410, ts5usbc410i) v d = 0 to 16 v t rise and t fall (10% to 90 %) = 100 ns r l = 50 ? switch on or off oe = 0 v 0 9 v v clamp_t maximum ovp transient duration above 5 v (ts5usbc412, ts5usbc412i) v d = 0 to 18 v t rise and t fall (10% to 90 %) = 100 ns r l = open c l = 10pf switch on or off oe = 0 v 60 95 ns v clamp_t maximum ovp transient duration above 5 v (ts5usbc412, ts5usbc412i) v d = 0 to 18 v t rise and t fall (10% to 90 %) = 100 ns r l = 50 ? c l = 10pf switch on or off oe = 0 v 60 95 ns v clamp_t maximum ovp transient duration above 5 v (ts5usbc410, ts5usbc410i) v d = 0 to 16 v t rise and t fall (10% to 90 %) = 100 ns r l = open c l = 10pf switch on or off oe = 0 v 60 95 ns v clamp_t maximum ovp transient duration above 5 v (ts5usbc410, ts5usbc410i) v d = 0 to 16 v t rise and t fall (10% to 90 %) = 100 ns r l = 50 ? c l = 10pf switch on or off oe = 0 v 60 95 ns t en_ovp ovp enable time r pu = 10 k to vcc ( flt) c l = 35 pf refer to ovp timing diagram figure 0.6 3 s t rec_ovp ovp recovery time r pu = 10 k to vcc ( flt) c l = 35 pf refer to ovp timing diagram figure 1.5 5 s advance information
7 ts5usbc41 www.ti.com scds377 ? march 2018 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.6 dynamic characteristics t a = ? 40 c to +85 c (industrial), t a = 0 to 70 (standard),v cc = 2.3 v to 5.5v, gnd = 0v, typical values are at v cc = 3.3 v, t a = 25 c, (unless otherwise noted) parameter test conditions min typ max unit c off d+, d- off capacitance v d+/- = 0 or 3.3 v, oe = v cc f = 240 mhz switch off 1.2 1.6 3.2 pf d1+, d1-, d2+, d2- off capacitance v d+/- = 0 or 3.3 v, oe = v cc or oe = 0v with sel1, sel2 (switch not selected) f = 240 mhz switch off or not selected 1.2 1.5 3.0 pf c on io pins on capacitance (ts5usbc412, ts5usbc412i) v d+/- = 0 or 3.3 v, f = 240 mhz switch on 1.4 4.5 6.2 pf c on io pins on capacitance (ts5usbc410, ts5usbc410i) v d+/- = 0 or 3.3 v, f = 240 mhz switch on 1.4 4.8 6.5 pf o iso differential off isolation rl = 50 cl = 5 pf f = 100 khz refer to off isolation figure switch off -90 db rl = 50 cl = 5 pf f = 240 mhz refer to off isolation figure switch off -22 db x talk channel to channel crosstalk rl = 50 cl = 5 pf f = 100 khz refer to crosstalk figure switch on -90 db bw bandwidth (ts5usbc412, ts5usbc412i) rl = 50 ; refer to bw and insertion loss figure switch on 1.2 ghz bw bandwidth (ts5usbc410, ts5usbc410i) rl = 50 ; refer to bw and insertion loss figure switch on 1.1 ghz i loss insertion loss rl = 50 f = 240 mhz; refer to bw and insertion loss figure switch on -0.7 db 6.7 timing requirements t a = ? 40 c to +85 c (industrial), ta = 0 to 70 (standard),v cc = 2.3 v to 5.5v, gnd = 0v, typical values are atv cc = 3.3 v, t a = 25 c, (unless otherwisenoted) parameter test conditions min nom max unit t switch switching time between channels (sel1, sel2 to output) v d+/- = 0.8 v refer to tswitch timing figure r l = 50 ? , c l = 5 pf, v cc = 2.3 v to 5.5 v 0.45 1.2 s t on device turn on time ( oe to output) v d+/- = 0.8 v refer to ton and toff figure 140 250 s t off device turn off time ( oe to output) v d+/- = 0.8 v refer to ton and toff figure 0.75 1 s t sk(p) skew of opposite transitions of same output (between d+ and d-) v d+/- = 0.4 v refer to tsk figure r l = 50 ? , c l = 1 pf, v cc = 2.3 v to 5.5 v 9 50 ps t pd propagation delay v d+/- = 0.4 v refer to tpd figure r l = 50 ? , c l = 5 pf, v cc = 2.3 v to 5.5 v 130 180 ps advance information
8 ts5usbc41 scds377 ? march 2018 www.ti.com submit documentation feedback copyright ? 2018, texas instruments incorporated 6.8 typical characteristics v cc = 3.3 v t a = 25 c figure 1. on-resistance vs input voltage advance information v in , input voltage (v) r on , resistance ( : ) 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.5 5 5.5 6 6.5 7 7.5 8 d001
9 ts5usbc41 www.ti.com scds377 ? march 2018 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 parameter measurement information channel on, r on = v/i sink figure 2. on-state resistance (r on ) figure 3. off leakage figure 4. on leakage (1) all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 , t r < 500 ps, t f < 500 ps. (2) c l includes probe and jig capacitance. figure 5. t switch timing switch v d+/- v dx+/- a a i sink switch v d+/- v v d+/- sel r l c l r l c l v sel v sel v d2+/- t switch t switch 1.2 v 80 % 20 % 1.8 v v d+/- 0 v 0 v 0.8 v v sel v d1+/- t switch t switch 0.8 v 80 % 20 % 1.8 v v d+/- 0 v 0 v 1.2 v v d1+/- v d2+/- advance information switch v d+/- a
10 ts5usbc41 scds377 ? march 2018 www.ti.com submit documentation feedback copyright ? 2018, texas instruments incorporated parameter measurement information (continued) (1) all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 , t r < 500 ps, t f < 500 ps. (2) c l includes probe and jig capacitance. figure 6. t on , t off for oe figure 7. off isolation figure 8. cross talk switch network analyzer source signal 50 d+ 50 d- 50 50 50 50 switch network analyzer source signal 50 o 50 o d+ source signal 50 o 50 o d- 50 o 50 o advance information v d+/- oe r l c l v oe v oe v dx+/- t on 0.8 v 90 % 10 % 1.8 v v d+/- 0 v 0 v 1.2 v t off v cc 2.3 v
11 ts5usbc41 www.ti.com scds377 ? march 2018 submit documentation feedback copyright ? 2018, texas instruments incorporated parameter measurement information (continued) figure 9. bw and insertion loss figure 10. t en_ovp and t dis_ovp timing diagram (1) all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 , t r < 500 ps, t f < 500 ps. (2) c l includes probe and jig capacitance. figure 11. t pd advance information switch network analyzer source signal 50 50 d+ source signal 50 50 d- 50 50 v d+/- oe r l c l v oe v d+/- t en_ovp 18 v 0 v t rec_ovp flt v cc 0 v v pos_thld 10 % 10 % switch d+/- 50 50 t pd 50 % 50 % 0.4 v 0 v v d+/- 50 % 50 % 0.4 v 0 v t pd v dx+/-
12 ts5usbc41 scds377 ? march 2018 www.ti.com submit documentation feedback copyright ? 2018, texas instruments incorporated parameter measurement information (continued) (1) all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 , t r < 500 ps, t f < 500 ps. (2) c l includes probe and jig capacitance. figure 12. t sk switch d+ d- 50 o 50 o 50 o 50 o t sk 50 % 50 % 0.4 v 0 v v dx+ 50 % 50 % 0.4 v 0 v t sk v dx- 0.4 v 0 v v d+/- advance information
13 ts5usbc41 www.ti.com scds377 ? march 2018 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 detailed description 8.1 overview the ts5usbc41 is a bidirectional low-power dual port, high-speed, usb 2.0 analog switch with integrated protection for usb type-c systems. the device is configured as a dual 2:1 or 1:2 switch and is optimized for handling the usb 2.0 d+/- lines in a usb type-c system as shown in figure 13 . figure 13. usb type-c connector pinout the ts5usbc41 also works in traditional usb systems that need protection from fault conditions such as automotive and applications that require higher voltage charging. the device maintains excellent signal integrity through the optimization of both r on and bw while protecting the system with 0 v to 20 v (16v for ts5usbc410 and 20v for ts5usbc412) ovp protection. the ovp implementation is designed to protect sensitive system components behind the switch that cannot survive a fault condition where vbus is shorted the d+ and d- pins on the connector. 8.2 functional block diagram advance information d+ d- ovp control logic vcc v ovp sel2 oe flt d1+ d1- d2+ d2- switches sel1 6 m 6 m 6 m
14 ts5usbc41 scds377 ? march 2018 www.ti.com submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3 feature description 8.3.1 powered-off protection when the ts5usbc41 is powered off the i/os of the device remain in a high-z state. the crosstalk, off-isolation, and leakage remain within the electrical specifications . this prevents errant voltages from reaching the rest of the system and maintains isolation when the system is powering up. 8.3.2 overvoltage protection the ovp of the is designed to protect the system from d+/- shorts to vbus at the usb and usb type-c connector. figure 14 depicts a moisture short that would cause high voltage (16 v for ts5usbc410 or 20 v for ts5usbc412) to appear on an existing usb solution that could pass through the device and damage components behind the device. figure 14. existing solution being damaged by a short advance information existing solutions d+ d2- d- d1- d2+ d1+ d+ d- d- d+ cc2 cc1 uart usb usb vbus vbus vbus vbus sbu1 sbu2 m o i s t u r e 16 v / 20 v
15 ts5usbc41 www.ti.com scds377 ? march 2018 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) the ts5usbc41 will open the switches and protect the rest of the system by blocking the 16 v / 20 v as depicted in figure 15 . figure 15. protecting during a 16 / 20-v short figure 16 is a waveform showing the voltage on the pins during an over-voltage scenario. figure 16. overvoltage protection waveform advance information d+/- d1/d2 flt v ovp_thld 0 v 0 v 16 v / 20 v d+ d2- d- d1- d2+ d1+ d+ d- d- d+ cc2 cc1 vbus vbus vbus vbus sbu1 sbu2 16 v / 20 9grhvq?w reach rest of system m o i s t u r e 16 v / 20 v uart usb usb
16 ts5usbc41 scds377 ? march 2018 www.ti.com submit documentation feedback copyright ? 2018, texas instruments incorporated 8.4 device functional modes 8.4.1 pin functions table 1. function table oe sel1 sel2 d- connection d+ connection h x x high-z high-z l l l d- to d1- d+ to d1+ l l h d- to d1- d+ to d2+ l h l d- to d2- d+ to d1+ l h h d- to d2- d+ to d2+ advance information
17 ts5usbc41 www.ti.com scds377 ? march 2018 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information there are many usb applications in which the usb hubs or controllers have a limited number of usb i/os or need to route signals from a single usb connector. the ts5usbc41 solution can effectively expand the limited usb i/os by switching between multiple usb buses to interface them to a single usb hub or controller or route signals from on connector to two different locations. with independent control of the two switches using sel1 and sel2, ts5usbc41 can be used to cross switch single ended signals. 9.2 typical application ts5usbc41 usb/uart switch. the ts5usbc41 is used to switch signals between the usb path, which goes to the baseband or application processor, or the uart path, which goes to debug port. the ts5usbc41 has internal 6-m ? pull-down resistors on sel1, sel2, and oe. the pull-down on sel1 and sel2 pins ensure the d1+/d1- channel is selected by default. the pull-down on oe enables the switch when power is applied. figure 17. typical application 9.2.1 design requirements design requirements of usb 1.0,1.1, and 2.0 standards must be followed. the ts5usbc41 has internal 6-m ? pulldown resistors on sel1, sel2, and oe, so no external resistors are required on the logic pins. the internal pull-down resistor on sel1 and sel2 pins ensures the d1+ and d1- channels are selected by default. the internal pull-down resistor on oe enables the switch when power is applied to vcc. 9.2.2 detailed design procedure the tts5usbc41 can be properly operated without any external components. however, ti recommends that unused pins must be connected to ground through a 50- resistor to prevent signal reflections back into the device. ti does recommend a 100-nf bypass capacitor placed close to ts5usbc41vcc pin. usb vcc d1- d2+ ovp logic control gnd vbus dp_t dp_b dm_t dm_b gnd usb connector uart usb d2- sel1sel2 oe flt d1+ v cc 100 nf advance information
18 ts5usbc41 scds377 ? march 2018 www.ti.com submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) 9.2.3 application curves figure 18. high speed eye diagram with ts5usbc41 figure 19. high speed eye diagram without ts5usbc41 10 power supply recommendations power to the device is supplied through the vcc pin and must follow the usb 1.0, 1.1, and 2.0 standards. ti recommends placing a 100 nf bypass capacitor as close to the supply pin vcc as possible to help smooth out lower frequency noise to provide better load regulation across the frequency spectrum. 0.0 0.5 1.0 1.5 2.0 -0.2 -0.4 0.0 0.4 0.2 time (ns) differential signal (v) 0.0 0.5 1.0 1.5 2.0 -0.2 -0.4 0.0 0.4 0.2 time (ns) differential signal (v) advance information
19 ts5usbc41 www.ti.com scds377 ? march 2018 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 layout 11.1 layout guidelines 1. place supply bypass capacitors as close to vcc pin as possible and avoid placing the bypass caps near the d traces. 2. the high-speed d must match and be no more than 4 inches long; otherwise, the eye diagram performance may be degraded. a high-speed usb connection is made through a shielded, twisted pair cable with a differential characteristic impedance. in layout, the impedance of d+ and d ? traces must match the cable characteristic differential impedance for optimal performance. 3. route the high-speed usb signals using a minimum of vias and corners which reduces signal reflections and impedance changes. when a via must be used, increase the clearance size around it to minimize its capacitance. each via introduces discontinuities in the signal ? s transmission line and increases the chance of picking up interference from the other layers of the board. be careful when designing test points on twisted pair lines; through-hole pins are not recommended. 4. when it becomes necessary to turn 90 , use two 45 turns or an arc instead of making a single 90 turn. this reduces reflections on the signal traces by minimizing impedance discontinuities. 5. do not route usb traces under or near crystals, oscillators, clock signal generators, switching regulators, mounting holes, magnetic devices or ics that use or duplicate clock signals. 6. avoid stubs on the high-speed usb signals due to signal reflections. if a stub is unavoidable, then the stub must be less than 200 mm. 7. route all high-speed usb signal traces over continuous gnd planes, with no interruptions. 8. avoid crossing over anti-etch, commonly found with plane splits. 9. due to high frequencies associated with the usb, a printed circuit board with at least four layers is recommended; two signal layers separated by a ground and power layer as shown in figure 20 . figure 20. four-layer board stack-up the majority of signal traces must run on a single layer, preferably signal 1. immediately next to this layer must be the gnd plane, which is solid with no cuts. avoid running signal traces across a split in the ground or power plane. when running across split planes is unavoidable, sufficient decoupling must be used. minimizing the number of signal vias reduces emi by reducing inductance at high frequencies. signal 1 gnd plane power plane signal 2 advance information
20 ts5usbc41 scds377 ? march 2018 www.ti.com submit documentation feedback copyright ? 2018, texas instruments incorporated 11.2 layout example figure 21. layout example c3 c2 c1 b1 a2 a2 a1 d+ b2 c4 b4 a3 b3 d- top layer 1 (signal1) inner layer 2 (gnd) inner layer 3 (vcc) bottom layer 4 (signal2) example 4 layer pcb stackup via to layer 2 (gnd) via to layer 3 (vcc) d2+ d2- d1+ d1- via to layer 4 (signal) sel1 sel2 vcc flt# oe# gnd place near vcc pin. advance information
21 ts5usbc41 www.ti.com scds377 ? march 2018 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation see the following: ? usb 2.0 board design and layout guidelines ? high-speed layout guidelines application report ? high-speed interface layout guidelines 12.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks e2e is a trademark of texas instruments. usb type-c is a trademark of usb implementers forum. all other trademarks are the property of their respective owners. 12.4 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 26-mar-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples XTS5USBC410YFFR preview dsbga yff 12 3000 tbd call ti call ti 0 to 70 xts5usbc410yfft preview dsbga yff 12 250 tbd call ti call ti 0 to 70 xts5usbc412yffr preview dsbga yff 12 3000 tbd call ti call ti 0 to 70 xts5usbc412yfft preview dsbga yff 12 250 tbd call ti call ti 0 to 70 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 26-mar-2018 addendum-page 2
www.ti.com package outline c 0.625 max 0.30 0.12 1.2 typ 0.8 typ 0.4 typ 0.4 typ 12x 0.3 0.2 b e a d dsbga - 0.625 mm max height yff0012 die size ball grid array 4222191/a 07/2015 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. ball a1 corner seating plane ball typ 0.05 c b 1 2 3 0.015 c a b symm symm a c d scale 8.000
www.ti.com example board layout 12x ( )0.23 (0.4) typ (0.4) typ ( ) metal 0.23 0.05 max solder mask opening metal under solder mask ( ) solder mask opening 0.23 0.05 min dsbga - 0.625 mm max height yff0012 die size ball grid array 4222191/a 07/2015 notes: (continued) 3. final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. for more information, see texas instruments literature number snva009 (www.ti.com/lit/snva009). symm symm land pattern example scale:30x c 1 2 3 a b d non-solder mask defined (preferred) solder mask details not to scale solder mask defined
www.ti.com example stencil design (0.4) typ (0.4) typ 12x ( 0.25) (r ) typ0.05 metal typ dsbga - 0.625 mm max height yff0012 die size ball grid array 4222191/a 07/2015 notes: (continued) 4. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. symm symm c 1 2 3 a b d solder paste example based on 0.1 mm thick stencil scale:30x
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own risk. designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. designer will fully indemnify ti and its representatives against any damages, costs, losses, and/or liabilities arising out of designer ? s non- compliance with the terms and provisions of this notice. mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2018, texas instruments incorporated

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